Integrated circuitry may comprise multiple levels of stacked wiring. The levels may include signal lines alternately arranged with shield lines. The shield lines may be utilized to alleviate cross-talk between adjacent signal lines. An example configuration comprising three stacked wiring layers is shown in FIG. 1. Specifically, the configuration shows a first wiring layer (i.e., first wiring level) M1, a second wiring layer (i.e., second wiring level) M2, and a third wiring layer (i.e., third wiring level) M3; with M3 being over M2 which in turn is over M1. Although three wiring layers are shown, it is to be understood that there may be other wiring layers below the illustrated wiring layers and/or above the illustrated wiring layers. Also, although the illustrated wiring layers are labeled M1-M3, if other wiring layers are present the shown layers may be M2-M4; M3-M6; etc., depending on the number of wiring layers beneath the illustrated wiring layers.
Each of the illustrated wiring layers comprises signal lines alternately arranged with shield lines. It may be desired for the shield lines within one wiring layer to be electrically connected with shield lines of other wiring layers vertically offset from said one wiring layer. For instance, it may be desired for the shield lines within wiring layer M2 to be electrically connected with the shield lines within wiring layer M1 and the shield lines within wiring layer M3, as such may alleviate coupling noises between the vertically-stacked wiring layers.
Connection of shield lines from wiring layer M2 with those of wiring layer M1 is relatively straightforward since the lines within wiring layer M1 run perpendicular to the lines within wiring layer M2. However, the connection of shield lines from wiring layer M2 with those of wiring layer M3 is problematic since the lines within wiring layer M2 run parallel to the lines within wiring layer M3, and the shield lines are staggered in wiring layer M2 relative to wiring layer M3. Thus, there is no vertical overlap between the shield lines of wiring layer M2 with those of wiring layer M3.
It is desirable to develop architectures which enable coupling between shield lines of stacked wiring layers of the type illustrated as wiring layers M2 and M3 in FIG. 1.
A prior application (U.S. application Ser. No. 15/155,334; currently assigned to Micron Technology, Inc of Boise, Id.; having Makoto Sato as the inventor; and filed May 16, 2016) discloses example architectures for coupling shield lines of wiring layer M2 with shield lines of wiring layer M3. Such architectures are described in FIGS. 2, 3A and 3B. The architectures are labeled “PRIOR ART” in that they predate the present application, but may not be strictly “prior art” for purposes of ascertaining novelty and obviousness of the claims of the present application in that the prior application and the present application are both presently assigned to the same entity (Micron Technology, Inc.), and have an inventor in common (Makoto Sato).
FIG. 2 shows an assembly 300 comprising the wiring layers M1, M2 and M3 stacked one atop another, and shows the wiring layers an exploded view. The lines within wiring layer M3 (shield lines 306 and signal lines 307) are shown to be slightly thicker than the lines within wiring layers M2 (shield lines 308 and signal lines 309) and M1 (shield lines 312 and signal lines 313). In practice the lines within wiring layers M1-M3 may all be the same thickness or some lines may be of different thickness relative to other lines, depending on the application.
The assembly 300 of FIG. 2 comprises a connecting region 302 which encompasses interconnects 304 (only some of which are labeled) at locations where portions of shield lines 306 of wiring layer M3 vertically overlap portions of the shield lines 308 of level M2. The interconnects 304 are shown as square features to diagrammatically represent the interconnects, but in other applications the interconnects 304 may have other shapes.
The shield lines 312 of wiring layer M1 are electrically coupled with the shield lines 308 of wiring layer M2 through vertical interconnects 310 (only some of which are labeled). The interconnects 310 are shown as circular features to diagrammatically represent the interconnects 310 and to enable interconnects 310 to be readily distinguished from interconnects 304 in the illustration of FIG. 2, but in other applications the interconnects 310 may have other shapes.
FIGS. 3A and 3B show assembly 300 in an alternative diagrammatic illustration. Specifically, the assembly 300 is shown in top view in FIG. 3A, with the lines of the wiring layers being heavily compressed. An expanded region of the top wiring layer M3 is shown in cross-sectional side view in FIG. 3B to assist the reader in understanding the top view of FIG. 3A. An approximate location of the illustrated portion of FIG. 2 is diagrammatically illustrated in FIG. 3A as corresponding to region labeled “FIG. 2”. The connecting region 302 is diagrammatically illustrated with a line traversing the top view of FIG. 3A.
A continuing goal of semiconductor fabrication is to increase circuit density (i.e., to increase the level of integration). A problem with the architecture of FIGS. 2, 3A and 3B is that there may be a large distance along individual shield lines of a given wiring layer (e.g., shield lines 306 of wiring layer M3) between the interconnects (304 of FIG. 2) utilized to couple the shield lines to shield lines of other wiring layers (e.g., shield lines 308 of wiring layer M2, shown in FIG. 2). Such problem is illustrated in the top view of FIG. 3A with an arrow 320 indicating a pitch between interconnects (i.e., a via-bypass pitch). The arrow 320 is open-ended to indicate that the full via-bypass pitch is not visible in the top view of FIG. 3A.
The signal lines (e.g., signal lines 307 of wiring layer M3, signal lines 309 of wiring layer M2, etc.) are coupled with associated buses (i.e., electrical pathways), and the number of signal lines coupled with an individual bus may be correlated with the via-bypass pitch.
As circuit density increases, there may be an increasing demand on the shield lines (e.g., increased voltage along the shield lines and/or increased current along the shield lines). Also, increased density of signal lines may lead to increased resistance along the signal lines and the associated buses. Accordingly, it would be desired to develop new architectures which reduce distances between interconnects coupling shield lines of one wiring layer to the shield lines of another wiring layer, and which reduce resistances along the signal lines and associated buses.